Infosys在阅读器中打开 / AI 翻译

EL5122 | 2-Channel Incremental Encoder Interface, 5 V single-ended (TTL, Open Collector) · 0 次阅读

Lock counter value

The gate function enables locking of the counter (0x60n0:11).
The counter is locked at the first pulse at the Gate/Latch input. Subsequent pulses have no influence on the counter value. This allows a timeframe to be defined in which counting signals are acquired. The gate function can be triggered by:

Lock counter value via a positive/negative edge at the gate/latch combination input (Enable pos./neg. gate)

  • The level at the gate/latch combination input at which the counter value is locked during runtime can be specified via index 0x80n0:04 "Gate polarity".
    • 0: Disable gate
      The gate/latch combination input is deactivated to disable the counter. It can still be used as external latch input for storage.
    • 1: Enable pos. gate
      The counter value is locked with HIGH level at the gate/latch combination input.
    • 2: Enable neg. gate
      The counter value is locked with LOW level at the gate/latch combination input
  • The current level at the gate/latch combination input is displayed via process record 0x60n0:0C "Status of input gate".

Locking the counter value via a PLC variable (Set software gate)

The counter value can be locked from the PLC application.

  • Index 0x70n0:09 "Set software gate" = TRUE
    The counter is locked.
  • For confirmation the "Software gate valid" bit (0x60n2:11) is set to TRUE.
  • Index 0x70n0:09 "Set software gate" = FALSE
    The counter is unlocked.
Lock counter value 1:

Activation of gate and latch functions via the same edge at the gate/latch input

When the gate function and a latch function is activated via the same edge at the gate/latch input, the latch function is always executed first, after which the counter value is disabled via the gate function.

Example:

Index 0x80n0:04 "Gate polarity" (1 = "Enable pos. gate") and

index 0x80n0:02 "Enable extern reset" = 1 with 0x80n0:10 "Extern reset polarity" = 1 (reset on positive edge at the gate/latch input)

With a positive edge at the gate/latch input the current counter value is first set to zero (reset). The counter value is then blocked.

The same applies to the use of index 0x80n0:04 "Gate polarity" (2 = "Enable neg. gate") and simultaneous activation of index 0x80n0:02 "Enable extern reset" with 0x80n0:10 "Extern reset polarity" = 0 (reset on negative edge at the gate/latch input).