Infosys在阅读器中打开 / AI 翻译

EL5042 | 2 Channel BiSS-C Interface · 0 次阅读

Parametrization as BiSS-C master

  • BiSS-C mode (0x80p8:18)
    • In the object 0x80p8:18 Mode: BiSS-C (0x00) need to be selected.
  • CRC polynomial (0x80p8:11)
    • The transmission of the data is CRC-secured. The counter polynomial for CRC determination is slave specific. Is the CRC transmitted inverted, the 0x80p8:03 “CRC invert” need to be set to TRUE.
  • Clock frequency (0x80p8:13)
    • Clock rate, limitations by the max. cable length need to be considered. A runtime compensation for the clock and data line is implemented, therefore the use of long cables and high data rates is possible (max. 10 MHz).
  • Multiturn [Bit] (0x80p8:15)
    • Number of multiturn bits provided by the slave. If only singleturn bits are provided (e. g. linear encoder) the value can be set to 0.
  • Singleturn [Bit] (0x80p8:16)
    • Number of singleturn bits provided by the slave.
  • Offset LSB Bit [Bit] (0x80p8:17)
    • Right aligned offset bits (null bits) can be set, if available (slave specific). The position data is shifted by the number of the offset bits.
Parametrization as BiSS-C master 1:

Note about the counter polynomial

The counter polynomial for the CRC determination is manufacturer-specific.
Common values are 0x43hex (67dec) or 0x97hex (151dec).
This value can be entered directly in the object 0x80p8:11.
The calculation of the polynomial and the cyclical data check between master and slave are carried out automatically.

The BiSS-C frame structure is following:

Offset MSB Bit (optional)

Position

[max. 64 Bit]

Offset LSB Bit
(optional)

Error

[1Bit]

Warning

[1Bit]

CRC

[8Bit]

Not relevant

Multiturn data

Singleturn data

Optional

Status Bits

CRC polynomial

0x80p8:15
Multiturn

0x80p8:16
Singleturn

0x80p8:17
Offset LSB Bit (right aligned)

0x80p8:02
Disable Status Bits = TRUE; bits will not be analyzed separately

0x80p8:11
CRC Polynomial