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KL5101/KS5101 | Incremental encoder interface · 0 次阅读

Register description

The registers can be read or written via the register communication. They are used for the parameterization of the terminal.

R0 to R7: Registers in the internal RAM of the terminal

The process variables can be used in addition to the actual process image. Their function is specific to the terminal.

  • R0 to R5: reserved
  • R6: Diagnostic register
    The diagnostic register can contain additional diagnostic information. Parity errors, for instance, that occur in serial interface terminals during data transmission are indicated here.
  • R7: Command register
    High-Byte_Write = function parameter
    Low-Byte_Write = function number
    High-Byte_Read = function result
    Low-Byte_Read = function number

R8 to R15: Registers in the internal ROM of the terminal

The type and system parameters are hard programmed by the manufacturer, and the user can read them but cannot change them.

  • R8: Terminal type
    The terminal type in register R8 is needed to identify the terminal.
  • R9: Software version (X.y)
    The software version can be read as a string of ASCII characters.
  • R10: Data length
    R10 contains the number of multiplexed shift registers and their length in bits.
    The Bus Coupler sees this structure.
  • R11: Signal channels
    Related to R10, this contains the number of channels that are logically present. Thus for example a shift register that is physically present can perfectly well consist of several signal channels.
  • R12: Minimum data length
    The particular byte contains the minimum data length for a channel that is to be transferred. If the MSB is set, the control and status byte is not necessarily required for the terminal function and is not transferred to the control, if the Bus Coupler is configured accordingly.
  • R13: Data type register

Data type register

Meaning

0x00

Terminal with no valid data type

0x01

Byte array

0x02

Structure 1 byte n bytes

0x03

Word array

0x04

Structure 1 byte n words

0x05

Double word array

0x06

Structure 1 byte n double words

0x07

Structure 1 byte 1 double word

0x08

Structure 1 byte 1 double word

0x11

Byte array with variable logical channel length

0x12

Structure 1 byte n bytes with variable logical channel length (e.g. 60xx)

0x13

Word array with variable logical channel length

0x14

Structure 1 byte n words with variable logical channel length

0x15

Double word array with variable logical channel length

0x16

Structure 1 byte n double words with variable logical channel length

  • R14: reserved
  • R15: Alignment bits (RAM)
    The alignment bits are used to place the analog terminal in the Bus Coupler on a byte boundary.

R16 to R30: Manufacturer parameter area (SEEROM)

The manufacturer parameters are specific for each type of terminal. They are programmed by the manufacturer, but can also be modified by the controller. The manufacturer parameters are stored in a serial EEPROM in the terminal, and are retained in the event of voltage drop-out.

These registers can only be altered after a code word has been set in R31.

R31 to R47: User parameter area (SEEROM)

The user parameters are specific for each type of terminal. They can be modified by the programmer. The user parameters are stored in a serial EEPROM in the terminal, and are retained in the event of voltage drop-out. The user area is write-protected by a code word.

Register description 1:

• R31: Code word register in RAM

The code word 0x1235 must be entered here so that parameters in the user area can be modified. If any other value is entered into this register, the write-protection is active. When write protection is not active, the code word is returned when the register is read. If the write protection is active, the register contains a zero value.

  • R32: Feature register
    [0x2200]
    This register specifies the operation modes of the terminal.
    The default values are shown in square brackets.

Feature bit no.

 

Description of the operation mode

Bit 0

0

  • reserved, do not modify!

Bit 1

0/1

  • 0: Counter inhibit with high-level at the gate input [0]
  • 1: Counter inhibit with low-level at gate input

Bit 2, Bit 3

00

  • Status input (active-low) is mapped into status byte 5 (ST.5) [00]

01

  • reserved

10

  • ST.5 = Status input, ST.6 = Status input

11

  • ST.5 = Status input, ST.6 = !Status input

Bit 4 - Bit6

000

  • External Latch function active [000]

001

  • Period measurement active

010

…

111

  • reserved

Bit 7 - Bit 9

0

  • reserved, do not modify!

Bit 10, Bit 11

00

4-fold evaluation of the encoder signals A, B, C, i.e. both rising and falling edges of the encoder signals A, B are counted. [00]

01

1-fold evaluation of the encoder signals A, B, C, i.e. each period of the encoder signal A is counted.

10

2-fold evaluation of the encoder signals A, B, C, i.e. each edge of the encoder signal A is counted.

11

4-fold evaluation of the encoder signals A, B, C

Bit 12 - Bit 14

0

  • reserved, do not modify!

Bit 15

0/1

0: Encoder Interface [0]

1: Counter mode is active.
16-bit up/down counter
Input A: Counter
Input B: Counting direction (5 V or open = up, 0 V = down)
Input C: Latch

  • R33 - R47
    Registers that depend on the terminal type.
  • R47 - R63
    Extended registers with additional functions.