Parametrization as SSI master
- SSI mode (0x80p8:18)
- In the Object 0x80p8:18 Mode: SSI (0x01) need to be selected.
- CRC polynomial (0x80p8:11) is automatically set to 0.
- Status Bits are automatically disabled (0x80p8:02 set to TRUE).
Notice | |
Possible impairment of devices! If the object 0x80n8:11 “CRC polynomial” is set to “0”, the data transmission is not CRC secured anymore. Therefore wrong counter values may not be detected by the encoder! |
- Clock frequency (0x80p8:13)
- Clock rate, limitations by the max. cable length need to be considered. Max. Frequency for SSI 2 MHz, slave specific
- Multiturn [Bit] (0x80p8:15)
- Number of multiturn bits provided by the slave. If only singleturn bits are provided (e.g. linear encoder) the value can be set to 0.
- Singleturn [Bit] (0x80p8:16)
- Number of singleturn bits provided by the slave.
- Offset LSB Bit [Bit] (0x80p8:17)
- Right aligned offset bits (additional bits, which should be blend out of the SSI frame) can be set, if available (slave specific). The position data is shifted by the number of the offset bits.
The SSI frame structure is following:
Position [max. 64 Bit] | Offset LSB Bit | Error [1Bit] | Warning [1Bit] | |
|---|---|---|---|---|
Multiturn data | Singleturn data | Optional | Status Bits, disabled per default | |
0x80p8:15 | 0x80p8:16 | 0x80p8:17 | 0x80p8:02 | |
Are additional bits in the SSI frame available (e.g. parity bit or power good bit), and should these bits be blended out, offset bits (0x80p8:17) can be set. The position data is than shifted by the number of the offset bits.